By Nicolas Sklavos, Ricardo Chaves, Giorgio Di Natale, Francesco Regazzoni
This e-book offers a entire creation to defense, from specification to implementation. functions mentioned comprise embedded structures starting from small RFID tags to satellites orbiting the earth. The authors describe a layout and synthesis movement, in an effort to rework a given circuit right into a safe layout incorporating counter-measures opposed to fault assaults. for you to handle the clash among testability and defense, the authors describe cutting edge design-for-testability (DFT) computer-aided layout (CAD) instruments that aid safeguard demanding situations, engineered for compliance with present, advertisement instruments. safe protocols are mentioned, which guard entry to invaluable try infrastructures and let the layout of safe entry controllers.
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Additional resources for Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment
P. 407–30. 4. Schlösser A, Nedospasov D, Krämer J, Orlic S, Seifert J-P. Simple photonic emission analysis of AES. In: Cryptographic hardware and embedded systems—CHES 2012. Springer; 2012. p. 41–57. 5. Barenghi A. Bertoni GM, Breveglieri L, Pelosi G. A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA. J Syst Softw. 2013;86(7):1864– 78. 6. Selmane N, Guilley S, Danger J-L. Practical setup time violation attacks on AES. In: Seventh European dependable computing conference, EDCC-7 2008, Kaunas, Lithuania, 7–9 May 2008, IEEE Computer Society; 2008.
On the other hand, local techniques are more precise in terms of fault location and model. However, this precision needs expensive equipment. The kind of fault injected can be defined as fault model. , location and impact. Location means the spatial and Fig. 1 An illustration of fault injection techniques 30 R. Piscitelli et al. temporal location of fault injection during the execution of target algorithm. Depending on the type and precision of the technique, location can be at the level of bit, variable or random.
Obtained results demonstrated that static timing analysis provides an effective way to estimate the worst case timings for the input lines of the state registers and pinpoint which ones are more likely to be vulnerable to setup-time violation attacks. 2 High-Level Simulation with Complex Fault Models High-level simulators are system simulator which simulate the behavior of a device with the precision of a clock cycle. They can be execution based, when the benchmark is directly executed, or trace based, when the simulation is carried out using a trace of execution previously generated.