Digital Signal Processing - Proakis Manolakis - Solutions by Saroja Srinidhi, John G. Proakis, Dimitris G. Manolakis

By Saroja Srinidhi, John G. Proakis, Dimitris G. Manolakis

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All addresses specify the byte at the start of the quantity. If an instruction needs 32 bits of data to be accessed in external memory, this is performed as two successive 16 bit accesses automatically. Instructions and operands are always 16 bits in size and accessed on word boundaries. Attempts to access instructions, operands, words or long words on odd byte boundaries cause an internal 'address' error. 42 Embedded systems design N ADDRESS I,,,~ A1 -A23 Vcc > i GND CLK ' DATA I FC0 FCl FC2 v D0-D 15 AS R/W UDS LDS DTACK MC68000 MPU m E BR BG VMA VPA BGACK BERR RESET IPL0 IPL1 HAU IPL2 The MC68000 pinout BYTE ADDRESS = BYTE ADDRESS = BYTE ADDRESS = 87 N BYTE 0 BYTE 1 N+2 BYTE 2 BYTE 3 N WORD 0 N+2 WORD 1 N+4 WORD 2 N N+2 LONG WORD 0 N+4 LONG WORD 1 N+6 N+8 LONG WORD 2 N+10 1 BYTE = 8 BITS 1 WORD = 16 BITS 1 LONG WORD = 32 BITS MC68000 data organisafion Function codes The function codes, FC0-FC2, provide extra information describing what type of bus cycle is occurring.

It embraces many techniques that are used to achieve superscalar performance that have appeared previously on RISC processors such as the MPC604 PowerPC chip. It was unique in that the device actually consisted of two separate die within a single ceramic pin grid array: one die is the processor with its level one cache on-chip and the second die is the level 2 cache which is needed to maintain the instruction and data throughput needed to maintain the level of performance. It was originally introduced at 133 MHz and gained some acceptance within high-end PC/workstation applications.

2 million 5 No Intel Pentium The Pentium is essentially an enhanced 80486 from a programming model. It uses virtually the same programming model and instruction set m although there are some new additions. The most noticeable enhancement is its ability to operate as a superscalar processor and execute two instructions per clock. To do this it has incorporated many new features that were not present on the 80486. As the internal architecture diagram shows, the device has two five-stage pipelines that allow the joint execution of two integer instructions provided that they are simple enough not to use microcode or have data dependencies.

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