By Harris D.M.
Electronic layout and machine structure is designed for classes that mix electronic good judgment layout with computing device organization/architecture or that educate those topics as a two-course series. electronic layout and computing device structure starts off with a contemporary technique by way of carefully protecting the basics of electronic common sense layout after which introducing Description Languages (HDLs). that includes examples of the 2 such a lot widely-used HDLs, VHDL and Verilog, the 1st half the textual content prepares the reader for what follows within the moment: the layout of a MIPS Processor. by means of the tip of electronic layout and desktop structure, readers may be in a position to construct their very own microprocessor and may have a top-to-bottom realizing of the way it works--even in the event that they haven't any formal heritage in layout or structure past an introductory type. David Harris and Sarah Harris mix an interesting and funny writing type with an up-to-date and hands-on method of electronic layout.
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11(a). 5: E ϭ A NOR R ϭ A ϩ R. 11(b) shows the NOR implementation. 3, we show that the two equations, A R and A ϩ R, are equivalent. The sum-of-products form provides a Boolean equation for any truth table with any number of variables. 12 shows a random threeinput truth table. 2) Unfortunately, sum-of-products form does not necessarily generate the simplest equation. 3 we show how to write the same function using fewer terms. qxd 1/31/07 9:55 PM Page 56 56 CHAPTER TWO A 0 0 1 1 R 0 1 0 1 Combinational Logic Design 2 .
20 THREE-INPUT NAND SCHEMATIC Draw a schematic for a three-input NAND gate using CMOS transistors. Y A B Solution: The NAND gate should produce a 0 output only when all three inputs are 1. Hence, the pull-down network should have three nMOS transistors in series. By the conduction complements rule, the pMOS transistors must be in parallel. 35; you can verify the function by checking that it has the correct truth table. 35 Three-input NAND Draw a schematic for a two-input NOR gate using CMOS transistors.
When transistors are in parallel, the network is ON if either transistor is ON. When transistors are in series, the network is ON only if both transistors are ON. The slash across the input wire indicates that the gate may receive multiple inputs. If both the pull-up and pull-down networks were ON simultaneously, a short circuit would exist between VDD and GND. The output of the gate might be in the forbidden zone and the transistors would consume large amounts of power, possibly enough to burn out.