Design of energy-efficient application-specific set by Tilman Glökler

By Tilman Glökler

After a short creation to low-power VLSI layout, the layout house of ASIP guide set architectures (ISAs) is brought with a different concentrate on very important positive aspects for electronic sign processing. according to the levels of freedom provided through this layout house, a constant ASIP layout stream is proposed: this layout circulation starts off with a given software and makes use of incremental optimization of the ASIP undefined, of ASIP coprocessors and of the ASIP software program by utilizing a top-down process and through employing application-specific variations on all degrees of layout hierarchy. A huge variety of real-world sign processing functions serves as car to demonstrate every one layout choice and offers a hands-on method of ASIP layout. eventually, entire case reports reveal the feasibility and the potency of the proposed technique and quantitatively assessment some great benefits of ASIPs in an business context.

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By using parallelized or pipelined processing units. Unfortunately, replication results in a higher power consumption, too, but the quadratic decrease of power consumption due to voltage scaling outweighs this increase in many practical cases like in [45]. A different approach is presented in [71], where the design is partitioned into critical regions with a small timing slack and uncritical regions with a high timing slack respectively using a dual supply voltage without affecting the critical path.

Furthermore, environmental concerns have triggered low-power initiatives like the Energy Star program [259]. Finally, the reliability of a system is increased by lowering the average power due to reduced thermal stress and reduced electromigration [191]. In the following subsections the sources for digital CMOS energy consumption, the energy estimation approaches and techniques to reduce the energy and power consumption are discussed. 3) Ptotal = Istandby Vdd + Ileakage Vdd + Isc Vdd + αavg Cl Vdd = Pstandby + Pleakage + Pshort circuit + Pcapacitive The standby current Istandby is typically completely avoided by a proper CMOS circuit style and can usually be neglected.

1 provides an overview of relevant academic and industrial ASIP designs and case studies. It has to be emphasized that most of the published ASIP case studies focus on performance rather than power optimization. An exception is the work of Kuulusa [152], which evaluates the effect of instruction set modifications on the power consumption, but without using more extensive architectural optimizations. 2. Previous Work 11 Authors, Affiliation and Reference Kuulusa, Tampere Univ. [152] B. , Philips Research [140] [162] A.

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